In the field of programmable logic controllers (PLCs), PLC processing was initially sequential in design. While effective and useful in supporting conventional industrial control and automation requirements, sequential PLCs do not generally support systems that require high speed automation processing. In response to this deficiency, external modules were developed to augment conventional PLC processing performance. The result is a system that provides parallel processing at speeds which exceed the typical sequential PLC and will support the high speed requirements demanded by current industrial control and automation systems.
PLC developers typically employ the use of certain circuit modeling programs to simulate the execution of a PLC program prior to imbedding the program within a PLC or within an external module that is in communication with the PLC. The circuit modeling programs are based upon the use of conventional ladder logic. It will be appreciated that FIG. 1 shows a conventional ladder logic diagram (using relay representation) for programming a PLC. A power conductor 5 is connected to input components 7 that are connected in series to an output component 10. One of ordinary skill in the art will understand that conventional ladder logic progresses sequentially from input to input and finally to output. The output component is then connected to a return path 14. The resultant ladder logic is converted into the discrete components that form the PLC. One of ordinary skill in the art will understand that since conventional ladder logic progresses sequentially it is extremely difficult and problematic to simulate the parallel processing provided by external modules that augment sequential PLCs.
FIGS. 2A and 2B show examples of conventional programming devices that a user may employ to program a PLC. FIG. 2A shows a dedicated device 17 that may be attached directly to the programming port of a PLC 20. Alternatively, a user may employ a standard personal computer 23 containing the appropriate software and connections 27 to program the PLC 20.
FIG. 3 provides a basic flow diagram 30 of the conventional method for programming a parallel execution PLC. In step 31 the PLC program is developed by the user utilizing program entry tools. The result is the program represented in a coding language, such as MC7, a Siemens Energy & Automation brand coding language. In step 32, the program is then simulated to detect logic and functional errors. The user corrects errors by entering changes using the program entry tools. It will be appreciated that during this step the user performs the laborious and time consuming task of determining and programming processing delays to account for race conditions that occur in the program. In step 33, the coding language is then compiled by a compiler into a native bit stream for the field programmable gate array (FPGA) and thereafter transferred in step 34 to a PLC. The PLC uses FPGA technology as its hardware engine to execute the instructions contained in the bit stream file.
As provided above, a problem that has often arisen in the circuit modeling and programming of PLCs is known as a race condition. In a sequential machine, such as a PLC, the program must ensure that downstream logic elements receive values at the proper time from upstream logic elements. When the timing is not correct, a race condition will occur. When a race condition exists, results of some logic paths will reach their outputs sooner than other paths. Consequently, the downstream elements might be strobed at a time when some of their inputs are not valid. When a race condition occurs, the program does not work properly and quite often will lead to errors in the output. One or ordinary skill in the art will understand that PLC programming that supports parallel processing generally causes an excessive amount of race conditions.
Conventionally, end users perform the onerous task of determining where the racing conditions exist and insert delays into key spots in the circuit to alleviate the race conditions manually. Users perform this task during the testing and debugging stage of the process. The task, known as alignment, is a tedious and time-consuming process. It would be advantageous to provide a system and method for preventing the occurrence of race conditions when programming PLCs. This system and method would be particularly beneficial for PLCs that are augmented with external modules which result in parallel processing.